Integrated circuit

ABSTRACT

An integrated circuit having a system base chip ( 1 ) that has basic functions for a transmitting and/or receiving system for a vehicle data bus, namely at least a system voltage supply ( 3 ), a system reset ( 3 ) and a monitoring function ( 2 ), an interface circuit ( 4, 5 ) that, in a self-contained fashion, runs at least parts of a data bus protocol, and in particular the LIN (Local Interconnect Network) protocol, that performs detection of the bit-rate of received data, and that is capable of passing on at least one received or transmitted byte. a serial/parallel converter ( 5 ) that makes use in its conversion of the bit-rate detected by the interface circuit ( 4, 5 ).

The invention relates to an integrated circuit having a system base chipof the kind usually provided for performing transmitting and/orreceiving functions at a node that is coupled to a vehicle data bus, toan interface circuit that is intended to run a data protocol for thevehicle bus and to a serial/parallel converter that converts the datathat is transmitted onto the data bus in serial form into parallel datathat can be subjected to further processing at the reception end.

A problem that always exists with the asynchronous transmission of datais that a receiver has to set itself to the clock frequency at which thedata is transmitted along the data bus. In what is called the LIN (LocalInterconnect Network) protocol for example, which is intended forvehicles, the data is transmitted from a master node to slave nodes, theslave nodes being able to synchronize themselves with the rate at whichthe data is transmitted.

To enable synchronization of this kind to take place to the data clockrate, the slave nodes have to be capable of recognizing certain symbolsthat differ from those employed by a standard SCI/UART (SerialCommunication Interface/Universal Asynchronous Receiver Transmitter)interface. This latter type of interface is one that is used as standardfor serial data transmission.

Hence, there is the problem that a user who wishes to make use ofautomatic synchronization to the clock rate cannot use a standardSCI/UART interface but has to specially adapt the interface. What isrequired for this purpose is a specially adapted microcontroller that isprovided as an external component and that has to assume responsibilityfor essential functions.

The consequence this has is that both the interface circuit and anexternally provided microcontroller have to be specially adapted to suitthe requirements.

It is an object of the invention to specify an integrated circuit thatis suitable for general-purpose use and is capable of performing thefunctions described above as a self-contained unit, i.e. with noexternal microcontroller.

This object is achieved by virtue of the features of claim 1:

An integrated circuit having

a system base chip that has basic functions for a transmitting and/orreceiving system for a vehicle data bus, namely at least a systemvoltage supply, a system reset and a monitoring function,

an interface circuit that, in a self-contained fashion, runs at leastparts of a data bus protocol, and in particular the LIN (LocalInterconnect Network) protocol, that performs detection of the bit-rateof received data, and that is capable of passing on at least onereceived or transmitted byte,

a serial/parallel converter that makes use in its conversion of thebit-rate detected by the interface circuit.

The integrated circuit according to the invention provides, in essence,three functional blocks. On the one hand, it provides the basicfunctions of a system base chip of the kind that is normally providedfor transceivers for vehicle data bus systems. These basic functionscomprise at least a system voltage supply, a system reset and amonitoring function such as, for example, a watchdog. The integratedcircuit further comprises an interface circuit that, in a self-containedfashion, runs at least parts of a data bus protocol, and in particularthe LIN (Local Interconnect Network) protocol. This interface circuit iscapable of performing bit-rate detection in a self-contained fashion. Itis also capable of passing on at least one byte that is received or isto be transmitted, i.e. of passing on a byte that has been received fromthe data bus to an external unit, to a microcontroller for example, orof receiving a byte from the latter and transmitting it along the databus. The integrated circuit further comprises a serial/parallelconverter that makes use in its conversion of the bit-rate detected bythe interface circuit.

An essential point in this case is that the integrated circuit performsthe functions described above in a self-contained fashion, i.e. can inparticular carry out the bit-rate detection without an externalmicrocontroller. It is true that a microcontroller of this kind isgenerally provided in applications, but it is not involved in thebit-rate detection and therefore does not have to be specially adaptedfor it. Hence, any available microcontroller can be used even when it isnot, in itself, suitable for bit-rate detection.

Because of the high integration of the circuit and the particularlybeneficial combination of functions, another advantage is that thepresent circuit performs all the functions that have to be proven andcertified for use on a data bus. For this reason, other elements thatare employed outside the integrated circuit according to the inventiondo not have to be certified separately.

In an embodiment of the invention that is detailed in claim 2, there isalso provided in the integrated circuit an RIC oscillator that acts as aclock-signal source for the circuit elements provided in the integratedcircuit and that also acts as a timebase for the bit-rate detection.

Advantageously, the clock signal generated by the RIC oscillator mayalso be provided to circuit elements outside the integrated circuit, forwhich provision is made in a further embodiment of the inventiondetailed in claim 3. It may with particular advantage be used for anexternally provided microprocessor.

As provided for by further embodiments of the invention detailed inclaims 4 and 5, the interface circuit may also receive and transmit notonly individual bytes but also complete messages that are transmittedalong the data bus. Such data may, if required, be buffer-stored in theinterface circuit.

The integrated circuit according to the invention is thus capable ofgeneral-purpose use even as a system base chip with interface andserial/parallel conversion for complete message transmission.

As already explained above, the data may be transmitted along the databus serially, in particular under the SCI/UART interface (SerialCommunication Interface/Universal Asynchronous Receiver Transmitter)standard. The serial/parallel converter in the integrated circuit isthen advantageously so arranged, as detailed in claim 6, that itreceives the data under this transmission standard and converts it intoparallel data, or vice versa.

These and other aspects of the invention are apparent from and will beelucidated with reference to the embodiments described hereinafter.

In the drawings:

The sole FIGURE of the drawing shows in a block circuit diagram anintegrated circuit 1 according to the invention and a microcontroller 7provided outside this integrated circuit 1.

The invention relates solely to the integrated circuit 1, which iscapable of performing a plurality of different functions in aself-contained fashion and which has for this purpose various blocks ofcircuitry that will be explained in what follows.

For this purpose, the integrated circuit 1 is so constructed that it canperform certain functions without the externally providedmicrocontroller 7, which latter in turn does not have to be speciallyadapted to the functions performed by the integrated circuit 1.

The integrated circuit 1 comprises as it were a system base chip of thekind provided in vehicle data bus systems. A system base chip of thiskind provides certain system functions, of which the integrated circuitaccording to the invention covers at least a system voltage supply, asystem reset and a monitoring function, in particular a watchdog.

For this purpose, there is provided in the integrated circuit 1 shown inFIG. 1 a voltage regulator 3 that converts a voltage BAT originatingfrom a vehicle battery (not shown) into a regulated voltage VCC. On theone hand, this regulated voltage is made use of within the integratedcircuit 1 but it may also be used for external system components such,for example, as the microcontroller 7.

The voltage controller 3 also supplies a reset signal RST that maylikewise be employed both in the integrated circuit 1 and, for example,in the microcontroller 7.

A monitoring function, that may, for example, take the form of awatchdog, is implemented in the block of circuitry marked 2 in theFIGURE, which also takes responsibility for other duties that will beexplained below. The watchdog may supply an interrupt signal that ismade available to the microcontroller 7.

The integrated circuit according to the invention further comprises aninterface circuit that on the one hand is capable of running, in aself-contained fashion, at least parts of a data-bus protocol. In theembodiment shown in the FIGURE, it is to be assumed that this is the LINprotocol, under whose rules data is transmitted onto a data bus that ismerely indicated in the FIGURE. The LIN (Local Interconnect Network)protocol makes provision for the data to be transmitted serially,essentially under the rules of the SCI/UART interface (SerialCommunication Interface/Universal Asynchronous Receiver Transmitter)standard. There are therefore provided in the integrated circuit 1 shownin the FIGURE a block of circuitry 4 and a block of circuitry 5, whichblocks, in essence, run the LIN protocol for data transmission. Theblock of circuitry 4 may also be referred to as a transceiver and isused to convert the analog data signal on the LIN line into a digitaldata signal and vice versa. The block of circuitry 5 is used to detectthe bit-rate in use on the LIN bus.

Provided in the LIN (Local Interconnect Network) protocol is a headerthat allows systems that receive data on the data bus to establish thebit-rate at which the data is transmitted and to synchronize themselvesto it. This bit-rate detection facility is often provided externally,i.e. is performed by means of the microcontroller 7, for example. Thishowever calls for the microcontroller 7 to be specially adapted. In theintegrated circuit 1 according to the invention, the bit-rate detectionis provided in a separate block of circuitry 5 to which the transceiver4 is coupled. The transceiver 4, when it receives a header of the kindmentioned, passes it on to the bit-rate detection facility 5, whichdetects the bit-rate by reference to a clock signal that is supplied byan R/C oscillator 6.

The particular advantage of this arrangement within the integratedcircuit 1 is that the microcontroller 7 does not have to be used forthis operation and consequently does not have to be adapted for thisfunction.

As soon as a valid header has been recognized by the LIN (LocalInterconnect Network) protocol 4, an appropriate measuring process isinitiated by means of the bit-rate detection facility 5 and the bit-rateis set accordingly for continuing reception.

Both the transceiver 4 and the bit-rate detection circuit 5 are capableof receiving or transmitting, and passing on as appropriate, individualbytes. If, for example, once bit-rate detection has taken place, such abyte is received by the transceiver 4, it is passed on to the bit-ratedetection facility 5 and by the latter to the block of circuitry 2 inwhich is provided, as well as the monitoring functions explained above,a serial/parallel converter. By means of this converter, the datareceived serially is converted into parallel data. The data receivedserially is generally transmitted under the SCI/UART (SerialCommunication Interface/Universal Asynchronous Receiver Transmitter)interface standard. The data that has been converted into parallel formis transmitted to an external unit, e.g. the microcontroller 7, via adata bus that is identified as SPI in the FIGURE.

The clock signal generated by the R/C oscillator, which is identified asClock in the FIGURE, is used both for the block of circuitry 2containing the serial/parallel converter and the watchdog circuit and,advantageously, for the externally provided microcontroller 7. Thissignal is also used as a timebase for the bit-rate detection.

The essential advantage of the integrated circuit 1 according to theinvention is, in essence, that, in a self-contained fashion, it iscapable of provided certain watchdog functions, of running at leastparts of the data transmission protocol, meaning the LIN (LocalInterconnect Network) protocol in the present case, of transmitting andreceiving individual items of data and of employing serial/parallelconversion of the data. The integrated circuit is able to performbit-rate detection in a self-contained fashion in this case and to makeuse thereof, where required, for the functions described above. Theintegrated circuit 1 is thus capable of general-purpose use and can becombined with any desired external components, which do not have to bespecially adapted to the functions described. In particular, themicrocontroller 7 may be a general-purpose microcontroller that does nothave to be specially modified for, for example, the bit-rate detection.

1. An integrated circuit having a system base chip that has basicfunctions for a transmitting and/or receiving system for a vehicle databus, namely at least a system voltage supply, a system reset and amonitoring function, an interface circuit that, in a self-containedfashion, runs at least parts of a data bus protocol, and in particularthe LIN (Local Interconnect Network) protocol, that performs detectionof the bit-rate of received data, and that is capable of passing on atleast one received or transmitted byte, a serial/parallel converter thatmakes use in its conversion of the bit-rate detected by the interfacecircuit.
 2. An integrated circuit as claimed in claim 1, characterizedin that there is provided in the integrated circuit an R/C oscillatorthat acts as a clock-signal source and as a timebase for the bit-ratedetection.
 3. An integrated circuit as claimed in claim 2, characterizedin that the clock signal generated by the R/C oscillator may also beprovided to circuits outside the integrated circuit, and in particularto a microprocessor.
 4. An integrated circuit as claimed in claim 1,characterized in that the interface circuit may also pass on completemessages.
 5. An integrated circuit as claimed in claim 1, characterizedin that the interface circuit performs buffer-storage of data receivedor to be transmitted.
 6. An integrated circuit as claimed in claim 1,characterized in that the serial/parallel converter converts serial dataconforming to the SCI/UART (Serial Communication Interface/UniversalAsynchronous Receiver Transmitter) interface standard into paralleldata, or vice versa.